1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to the number of lines divided and the number of contacts in a nonvolatile semiconductor memory device having a three-dimensional stacked structure.
2. Description of the Related Art
In recent years, a large-capacity and low-price nonvolatile semiconductor memory device such as a flash memory has expanded the use and market as a storage memory, for example, a memory card and a semiconductor drive device (the so-called SSD: Solid State Drive). The storage memory has been required to have a much larger capacity and lower cost and, for the purpose of realization, process dimensions have been reduced progressively. A flash memory of the conventional type, however, has a limit on the 20-30 nm generation as is said in the art and therefore nonvolatile semiconductor memory devices such as a ReRAM (Resistive RAM) and a PCRAM (Phase Change RAM) including resistive memory elements have received attention as successive candidates and have been developed progressively (Patent Document 1: JP 2002-541613T).
The PCRAM is also referred to as the phase change memory and changes the crystal structure of the resistive memory element, thereby changing the resistance of the element to store information. For example, when the memory element is to be changed to a high-resistance state, current is supplied to the element for heating, and then the element is quenched, thereby turning the crystal structure into the amorphous (non-crystalline) state. When the memory element is to be changed to a low-resistance state, current is supplied to the element for heating, and then the element is slowly cooled for crystallization. It has a characteristic in switching between the high-resistance state and the low-resistance state controllable with one directional current but a disadvantage on a relatively large current required in writing.
On the other hand, available examples of the resistive memory element utilized in the ReRAM include a transition metal oxide and so forth. The resistive memory element has two types of operation modes as known. One is referred to as the bipolar type, which switches the polarity of the voltage applied to the element between the normal and the reverse, thereby switching between the high-resistance state and the low-resistance state. The other is referred to as the unipolar type, which retains the polarity of the voltage applied to the element unchanged in one direction and controls the voltage value and application time of the voltage applied, thereby switching between the high-resistance state and the low-resistance state.
In the case of the memory element of the unipolar type, a memory cell configuration of the so-called 1D1R type, including a resistive memory element and a diode connected in series using no memory-cell selection transistor, can realize memory cells of the so-called cross-point type capable of arranging memory cells at intersections of bit lines and word lines. The memory cell of the cross-point type has a cell size as small as 4F2 and accordingly can realize a high-density memory cell array as an advantage.
Further, the memory cell of the cross-point type uses no selection transistor and accordingly allows memory cell arrays to be stacked relatively easy as an advantage. In the case of the stacked memory cell arrays, the area of the memory cell array is kept unchanged while the memory capacity (integration) can be made higher. Accordingly, it is possible to realize a larger capacity and a lower cost together. Further, the larger capacity can be achieved without fine patterning and accordingly the development costs can be reduced to realize the nonvolatile semiconductor memory device at lower costs.
Even if the memory cell arrays are stacked, however, transistors contained in circuits such as a sense amplifier and a row decoder are formed on a substrate like the prior art. Therefore, as for the contact regions for connecting the stacked bit lines and word lines with these circuits, the area of the contact regions increases as the number of stacked layers increases. This increases the chip area and prevents achievement of lower costs as a problem.